Appeal No. 2003-0836
Application No. 09/205,086
BACKGROUND
Appellants' invention is directed generally to a memory
controller including a refresh timing circuit that generates
clock pulses (specification, page 4). An understanding of the
invention can be derived from a reading of exemplary independent
claim 1 and dependent claim 3, which are reproduced as follows:
1. A computer system comprising:
a memory; and
a memory controller, wherein the memory controller includes
a refresh timing circuit for generating clock pulses used to
trigger memory refresh events.
3. The computer system of claim 2, wherein the refresh
timing circuit further comprises:
a clock generator for generating the clock pulses;
a first counter coupled to the clock generator;
a storage register coupled to the clock generator and the
counter; and
a comparator coupled to the clock generator, the counter and
the storage register.
The prior art reference of record relied upon by the
Examiner in rejecting the appealed claims is:
Direct Rambus Technology Disclosure (DRTD), pgs. 1-16,
(October 15, 1997).
Claims 1-28 and 38-49 stand rejected under 35 U.S.C.
§ 102(b) as being anticipated by DRTD.
Page 2
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007