Appeal No. 2003-0836
Application No. 09/205,086
In response, the Examiner argues that the RMC is a
controller for dynamic RAM (DRAM) which inherently requires
refreshing to maintain coherency of the stored data (answer, page
7). Examiner further states that the RMC can include an internal
clock generator (answer, page 4).
A rejection for anticipation under section 102 requires that
the four corners of a single prior art document describe every
element of the claimed invention, either expressly or inherently,
such that a person of ordinary skill in the art could practice
the invention without undue experimentation. See Atlas Powder
Co. V. Ireco Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947
(Fed. Cir. 1999); In re Paulsen, 30 F.3d 1475, 1478-79, 31 USPQ2d
1671, 1673 (Fed. Cir. 1994).
A review of DRTD reveals that the reference relates
generally to DRAM, memory controllers and a bus structure (DRTD,
page 7). The reference explicitly teaches that the RDRAMs only
respond to requests, and the RMC is the only device that
generates these requests (id.). Therefore, the RMC generated
request signals must include these refresh signals. Although the
reference in Figure 4 on page 8 shows that the RMC is connected
to an external clock, the reference on page 9 also discloses an
internal clock that “can be integrated in the memory controller.”
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