Appeal No. 2003-0836
Application No. 09/205,086
We also note Appellants’ argument that a memory controller
(MC) doesn’t inherently include a refresh timing circuit.
Appellants specifically argue that:
In fact prior art memory controllers, such as the RMC
disclosed in the Rambus Disclosure, receive clock pulses
from an external clock source in order to trigger a memory
refresh.
(brief, page 7).
This argument attempts to differentiate between implementing
internal and external clock sources. Not only does the reference
explicitly state, as discussed above, that the RMC may contain an
internal clock source, but also Appellants’ invention does appear
to include an external clock in addition to an internal clock
source to trigger a memory refresh. In fact, in contradiction to
Appellants’ own argument, the claimed invention’s internal clock
generator [432] is disclosed to utilize an external clock source
(labeled as host clk) in order to trigger a non-sleep memory
refresh instead of the already present internal clock source
(labeled as osclk) (Figs. 4, and 8; specification, pages 10, 11
and 14).
Therefore, we are unpersuaded by Appellants’ argument that
the timing circuitry in the RMC does not generate the timing
refresh pulse used to trigger memory refresh events. As
established above, the only requests received by the RDRAM are
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