Appeal No. 2004-0607
Application No. 09/792,848
23. An integrated circuit comprising:
a substrate;
a logic circuit element formed over said substrate;
a first triple well formed in said substrate under said
logic circuit element, said triple well including a first P-well
formed within a first N-well formed in said substrate, said first
P-well being positioned directly beneath said logic circuit
element, said first P-well being biased by a first bias potential
above Vss;
a radio frequency element formed over said substrate; and
a second triple well formed under said radio frequency
element, said second triple well including a second P-well
directly underneath said radio frequency element and said second
P-well formed in a second N-well, said first and second triple
wells being isolated from one another such that said N-well of
said first and second triple wells are spaced away from one
another to isolate the logic circuit element from the radio
frequency element, said second P-well being biased by a second
bias potential above Vss.
THE REFERENCES
References relied upon by the examiner
Momohara 6,055,655 Apr. 25, 2000
Zhu et al. (Zhu) 6,133,079 Oct. 17, 2000
Reference relied upon by the appellant
Neil H.E. Weste and Kamran Eshraghian (Weste), Principles of CMOS
VLSI Design - A Systems Perspective” (page unknown) (Addison-
Wesley 2nd ed. 1993).
THE REJECTIONS
The claims stand rejected as follows: claims 23-29 under
35 U.S.C. § 112, first paragraph, written description
requirement; claims 23-29 under 35 U.S.C. § 103 as obvious over
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