Appeal No. 2004-0607
Application No. 09/792,848
Accordingly, we affirm the rejection under 35 U.S.C. § 112, first
paragraph.
Rejections under 35 U.S.C. § 103
Momohara discloses an integrated circuit comprising a
substrate having formed thereover a logic circuit element
(processor 2) and an analog circuit element (7) (figure 22A).
There is no dispute as to whether Momohara’s disclosure of an
analog circuit element would have fairly suggested, to one of
ordinary skill in the art, the appellant’s radio frequency
element. The logic circuit element and the analog circuit
element are above separate triple wells, each triple well being a
P-well formed in an N-well in the P-substrate (figures 7
and 24).4 Both P-wells are biased by “low potential power VSS
(ground potential)” (col. 9, lines 31-33; col. 21, lines 35-37).
The examiner argues that “[o]ne has to guess the correlation
[in the appellant’s original disclosure] between the disclosed
potential bias Va and the claimed potential bias Vss. Thus,
appellant’s inadequacies in disclosing the relationship between
bias potential Va and the claimed bias potential Vss, render the
bias potential of Momohara as being identical to Va and above
4 The discussion of the processor in figures 6 and 7
(col. 9, lines 18-54) reasonably appears to apply to the
processor in figure 22.
6
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