Appeal No. 2004-0607
Application No. 09/792,848
bias must be above the lowest voltage power supply bias that is
available on the chip which is VSS” (brief, page 5). What the
specification states is (page 20, lines 9-13): “In some cases the
lower frequency performance may also be improved merely by
varying the bias (VA) applied to the P-well 46. In other words,
the higher the bias potential applied to the P-well 46, the
better the high frequency performance.” As pointed out by the
examiner (answer, page 8), this disclosure pertains to the
embodiment in figure 4 wherein the P-well is below inductor 50
and component 48 which appears to be a second inductor.3 The
appellant’s claim 23, however, requires that a P-well below a
logic circuit element (205; figure 19) is biased by a bias
potential above Vss. The specification does not indicate that
the disclosed benefit of increasing the bias to a P-well below
inductors applies to biasing a P-well below a logic circuit
element.
We therefore find that the appellant’s original disclosure
would not have conveyed with reasonable clarity to those skilled
in the art that, as of the filing date sought, the appellant was
in possession of a P-well biased by a bias potential above Vss.
3 Component 48 is not identified in the appellant’s
specification.
5
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