Ex Parte Tsai et al - Page 3




                    Appeal No. 2004-1123                                                                                                                                  
                    Application No. 09/933,503                                                                                                                            


                                                                             OPINION                                                                                      


                    In reaching our decision in this appeal, we have given                                                                                                
                    careful consideration to appellants' specification and claims, to                                                                                     
                    the applied prior art references, and to the respective positions                                                                                     
                    articulated by appellant and the examiner.  As a consequence of                                                                                       
                    our review, we have made the determination which follows.                                                                                             


                    In considering the examiner's rejection of claims 10 through                                                                                          
                    20 under § 103(a), we note that the "Background of the Invention"                                                                                     
                    portion of appellants' specification informs us that in the field                                                                                     
                    of semiconductor fabrication it has become desirable to operate                                                                                       
                    in an extremely high cleanliness minienvironment that eliminates                                                                                      
                    micro-contamination and reduces native oxide growth on silicon                                                                                        
                    surfaces.  Figure 1 of the application is designated "Prior Art"                                                                                      
                    and schematically shows such a high cleanliness minienvironment                                                                                       
                    (10).  Semiconductor wafers to be processed are transported into                                                                                      
                    the high cleanliness minienvironment via a standard mechanical                                                                                        
                    interface apparatus (SMIF) located at a loading and unloading                                                                                         
                    section (14).  More particularly, a cassette (30) of wafers is                                                                                        
                    transported into the high cleanliness minienvironment from a SMIF                                                                                     
                    pod (18) situated on top of the SMIF apparatus (20).                                                                                                  

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