Appeal No. 2004-1629
Application No. 09/507,204
through additional stages of the pipeline. The stored data is
later outputted such that it masks the regular output of those
stages.
Representative independent claim 1 is reproduced below:
1. A microprocessor based method of stalling pipeline
data, comprising:
a) upon initiation of a stall, allowing data that is to be
stalled to propagate through N more stages of a pipeline;
b) N cycles after the stall is initiated, causing data
output from a last of the N more stages to be stored in a
deferred stall register; and
c) N cycles after the stall is lifted, causing the data
stored in step b) to be output from the deferred stall register.
The Examiner relies on the following references in rejecting
the claims:
McLellan 5,325,495 Jun. 28, 1994
John B. Peatman (Peatman), “The design of Digital Systems,”
McGraw-Hill Book Company, p. 411 (1972).
Claims 1, 3, 4, 7, 8, 10-14, 17, 18 and 21 stand rejected
under 35 U.S.C. § 102(b) as being anticipated by McLellan.
Claims 2, 5, 6, 9, 19 and 20 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over McLellan.
Claims 15 and 16 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over McLellan and Peatman.
2
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