Appeal No. 2004-1629
Application No. 09/507,204
In response to Appellants’ arguments, the Examiner asserts
that McLellan does indeed provide for an “N cycle wait” by
teaching that “once a stall is initiated, data begins capturing
in a queue stage immediately” (answer, page 15). The Examiner
argues that “immediately means that data is captured at the start
of the next clock cycle after the stall is initiated” or if N=1,
there is one cycle wait between the time that the stall is
initiated and when data begins (id.). The Examiner further
explains that data from stage 3 will go N more stages from stage
3 to the Q-stage when N=1 (answer, pages 17).
A rejection for anticipation under section 102 requires that
the four corners of a single prior art document describe every
element of the claimed invention, either expressly or inherently,
such that a person of ordinary skill in the art could practice
the invention without undue experimentation. See Atlas Powder
Co. v. Ireco Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947
(Fed. Cir. 1999); In re Paulsen, 30 F.3d 1475, 1478-79, 31 USPQ2d
1671, 1673 (Fed. Cir. 1994).
After reviewing McLellan, we agree with Appellants’
assertion that the queue stage of the prior art cannot be equated
to both the claimed “N more stages” and “stall register.”
McLellan relates to a pipelines computer system in which a queue
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