Appeal No. 2004-1629
Application No. 09/507,204
stage receives the output of one stage when a stall occurs in the
next stage (abstract). Queue stage 16 is asserted when a
pipeline stall occurs in stage 4 or downstream during which stage
3 sends its output to the queue stage 16 to avoid stalling the
earlier pipeline stages (col. 5, lines 51-58). As depicted in
Figure 1 of McLellan, the position of queue stage 16 is such that
if N=1, the stalled data must be propagated one more stage to
queue stage 16, which becomes the “last of the N more stages” and
its data must be stored in a deferred stall register. Here the
data is already in queue stage 16 which cannot read on a stall
register to send the data output from the “last of the N more
stages.” For queue stage 16 to be a stall register after the
data is propagated at least one more stage, the stall must have
occurred in stage 2 or 1 which after one or two more stages the
data is stored in queue stage 16. However, in this case the data
output from queue stage 16 to stage 4 is not delayed by 1 or more
cycles and is sent to stage 4 without delay as soon as the stall
is removed.
Therefore, what the Examiner characterizes in McLellan as
the stall register and the propagation of the data after a stall
is initiated, cannot read on all of the claimed steps. Thus,
McLellan does not anticipate the claimed subject matter and the
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