Appeal No. 2004-1629
Application No. 09/507,204
We make reference to the answer (Paper No. 15, mailed
February 10, 2004) for the Examiner’s reasoning, and to the
appeal brief (Paper No. 14, filed November 12, 2003) and the
reply brief (Paper No. 16, filed April 8, 2004) for Appellants’
arguments thereagainst.
OPINION
With respect to the 35 U.S.C. § 102 rejection of claims 1,
3, 4, 7, 8, 10-14, 17, 18 and 21 as anticipated by McLellan,
Appellants point out that the prior art begins capturing data in
a queue stage immediately after a stall is initiated whereas the
claims allow data that is to be stalled to propagate through N
more stages before storing the data (brief, page 10). Appellants
further assert that if the queue stage 16 of McLellan (Figure 1)
is equated with claimed “N more stage,” then the reference lacks
a “stall register” for capturing the output from the “N more
stages” (brief, page 10). On the other hand, Appellants argue
that if the queue stage 16 of McLellan is characterized as the
claimed “deferred stall register,” then the reference does not
allow data to propagate through “N more stages” and instead, is
clocked into the queue stage (brief, page 10; reply brief,
page 2).
3
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007