Appeal No. 2005-1997 Page 3
Application No. 09/493,319
the form of a voltage) from a signal input line 12 to the capacitor 24 of the selected SLM
cell. (Id. at 2.)
Because the array might be large, explains the appellant, the number of signal
lines is smaller than the number of column lines. Consequently, the signal lines are
used to transfer a charge to "K" SLM cells at a time (where K, the number of signal
lines, is less than the M, the number of columns). Only the K column lines are driven
with the new charge; the remaining column lines are held in a tri-state condition and are
coupled to the unselected capacitors of the row. Unfortunately, asserts the appellant,
"charge sharing typically occurs between the capacitors 24 and the tri-stated column
lines 16." (Id. at 3.)
In contrast, Figure 2 of the specification shows the appellant's SLM cell 50.
Therein, a memory 66 stores a digital indication of a pixel intensity for a pixel cell 54.
A digital-to-analog converter ("DAC") 62 transforms the digital indication into an analog
voltage to refresh the charge of the SLM cell's capacitor 50. As shown in Figure 3 of the
specification, the SLM cell is one of several SLM cells 50 of a row. Because all the
capacitors 52 in the SLM cells of a row may be updated simultaneously, without
coupling any of the capacitors to a "tri-stated" column line, asserts the appellant, charge
sharing between the capacitors and the column lines does not occur. (Id. at 4.)
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