Appeal No. 2005-2512
Reexamination Control No. 90/006,431
C. Appellant’s claimed invention
The “Background” portion of the ‘952 patent explains that the invention “relates to
computer-aided design (CAD) tools for analyzing integrated circuits and, more
particularly, to analyzing power Vdd and ground nets in integrated circuits for
electromigration, voltage drop and ground bounce.” ‘952 Patent, col. 1, ll. 20-24. The
term “power net” refers to the wire connections between the power Vdd or ground pads
and the circuit elements. Id. at col. 3, ll. 47-50. The “Background” portion
contrasts the invention with known CAD tools as follows:
Numerous CAD tools exist for simulating transistor networks of ICs
(e.g., SPICE).[5] An innovative system is described in U.S. patent
application Ser. No. 08/040,531 [now Patent 5,446,676], entitled
"Transistor-Level Timing and Power Simulator and Power Analyzer", filed
Mar. 29, 1993 by Huang et al., and U.S. patent application Ser. No.
08/231,207 [abandoned], entitled "Power Diagnosis for VLSI Designs",
filed Apr. 21, 1994 by An-Chang Deng, which are both hereby
incorporated by reference for all purposes. However, none of the prior art
systems allow the user to simulate the power nets of an IC and display
5 As explained in one of the references relied on by the examiner, SPICE is a
copyright of the Board of Regents, University of California, Berkeley. See Archer
Systems, Inc., ARCADIA User Manual, Version 1.1 (Feb. 1995) (“Arcadia Manual”) at
iii.
4
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007