Appeal No. 2006-0910
Application No. 09/725,821
receives first, second, and third chaining variables from a
register file. A multiplexer receives a fourth chaining variable
when a first hash algorithm is being processed and receives a
zero value when a second hash algorithm is being processed.
Claim 1 is illustrative of the invention and reads as
follows:
1. An apparatus for selectively processing first and second
cryptographic hash algorithms, comprising:
a register file (12) having at least five registers for
storing chaining variables;
a function circuit (22) receiving first (B), second (C) and
third (D) chaining variables and an output that provides a
logical data value;
a first multiplexer (24) having an input coupled to the
register file for receiving a fourth (E) chaining variable and an
output that provides the fourth chaining variable when the first
cryptographic hash algorithm is being processed by the apparatus
and a zero value when the second cryptographic hash algorithm is
being processed by the apparatus; and
a summing circuit (30) having a first input coupled to the
output of the function circuit for receiving the logical data
value, a second input coupled to the output of the first
multiplexer, and an output coupled to the register file.
The Examiner relies on the following prior art:
Batcher 4,314,349 Feb. 02, 1982
Niehaus et al. (Niehaus) 4,399,517 Aug. 16, 1983
Masaki 4,739,195 Apr. 19, 1988
Turner et al. (Turner) 4,896,296 Jan. 23, 1990
Childs et al. (Childs) 5,623,545 Apr. 22, 1997
2
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007