Appeal No. 2006-1663
Application No. 09/871,883
in a “level of wiring.” (Answer 7). The Examiner then concludes that it would
have been obvious to “modify the lower interconnect wiring level of Farrar by
adding dielectric pillars as taught by Otsuka et al. to form a highly reliable
damascene wiring structure” as Otsuka teaches. (Answer 7).
Appellants argue that neither Farrar nor Otsuka discloses the claim feature
“lower conductive liner on [the] sides of said dielectric pillars.” Appellants also
argue the Examiner’s reason for combining Otsuka with Farrar (i.e., “to form a
highly reliable damascene wiring structure”) is not persuasive because Otsuka’s
improved reliability against void formation is not necessary in Farrar. Farrar uses
barrier layers 384 and 314 shown in Figure 3K to prevent void formation. (Br.
26-27). Appellants argue that adding dielectric pillars to Farrar would add an
unnecessary expense that Farrar specifically teaches to avoid. (Br. 27).
The Examiner responds that “Otsuka was cited to show that dielectric pillars
were formed in a wiring level to improve the structural integrity” of that level.
(Answer 12). Moreover, the Examiner determines that “since semiconductors
often have many wiring levels, and each wiring level essentially consists of the
same structures” one of ordinary skill would find that Otsuka’s insulating pillars
would also be useful in a lower wiring level. (Answer 12). Furthermore, the
Examiner states that Otsuka forms the insulating pillars (i.e., dielectric pillars) in a
conductor layer, which would be next to the liner and core conductor. (Answer
12). The Examiner then determines that, when Otsuka and Farrar are combined,
the barrier/adhesive layer 314 (i.e., lower conductive liner) would be on the side of
one or more insulating pillars (i.e., dielectric pillars) of Otsuka. (Supplemental
Examiner’s Answer 3).
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