Appeal No. 2006-1663
Application No. 09/871,883
Moreover, even if Otsuka’s insulating pillars (i.e., dielectric pillars) were to
be combined with Farrar’s interconnect structure; Appellants’ claimed structure
would not result. In Otsuka’s Figure 13C embodiment cited by the Examiner, the
insulating pillars P (i.e., dielectric pillars) are placed in the upper wiring 10.
(Otsuka, col. 12, ll. 30-35). Thus, when combined with Farrar, Otsuka’s Figure
13C embodiment indicates that the insulating pillars (i.e., dielectric pillars) would
be combined with Farrar’s second core conductor 344 (i.e., upper core conductor).
This teaching is contrary to the express claim language, which requires that the
dielectric pillars be “formed in said lower level wire.” The Examiner’s reasoning
that since semiconductors have many layers one would find it useful to place
Otsuka’s insulating pillars in a lower wiring level (Supplemental Examiner’s
Answer 2) appears to be based solely on impermissible hindsight.
For the foregoing reasons, the 35 U.S.C. § 103(a) rejection of claims 30 and
31 over Farrar in view of Otsuka cannot be sustained.
CLAIMS 32-33
Claims 32-33 depend from claim 31 and are likewise rejected under
35 U.S.C. § 103(a) over Farrar in view of Otsuka. Because claims 32 and 33
depend from claim 31, the rejections of these claims cannot be sustained for the
same reasons the rejection of claim 31 could not be sustained.
Accordingly, we reverse the 35 U.S.C. § 103(a) rejection of claims 32 and
33 over Farrar in view of Otsuka.
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