Appeal No. 2006-1901
Application No. 10/742,436
BACKGROUND
Appellants’ invention is directed to a method of protection
against single event upsets (SEUs) in a latch circuit which may
be caused by ionizing radiation. According to Appellants,
protecting against SEUs restores a latch output to its original
value or suppresses such transient signals (specification, page
4). An understanding of the invention can be derived from a
reading of exemplary independent claim 1, which is reproduced
bellow:
1. A latch circuit, comprising:
a first latch; and
a second latch to harden the latch circuit to a single event
upset, the second latch including a transmission gate including
two transistors, the transmission gate having an output port to
couple to only one transistor of the first latch.
The Examiner relies on the following prior art references:
Jamshidi et al. (Jamshidi) 5,646,558 Jul. 8, 1997
Zhang 6,026,011 Feb. 15, 2000
T. Calin et al. (Calin), “Upset Hardened Memory Design for
Submicron CMOS Technology,” IEEE Transactions on Nuclear Science,
Vol. 43, No. 6, December 1996, pp. 2874-2878.
Claims 1-3, 7-9 and 11 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Calin and Jamshidi.
2
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