Appeal No. 2006-1901
Application No. 10/742,436
F.3d 1350, 1355, 47 USPQ2d 1453, 1456 (Fed. Cir. 1998). However,
the motivation, suggestion or teaching may come explicitly from
statements in the prior art, the knowledge of one of ordinary
skill in the art, or, in some cases the nature of the problem to
be solved. See In re Dembiczak, 175 F.3d 994, 999, 50 USPQ2d
1614, 1617 (Fed. Cir. 1999).
From our review of Calin and Jamshidi, we find that both
references provide sufficient motivation for using two
transistors in a latch circuit when a higher level of reliability
is desired. In particular, Jamshidi describes complementary
switch pass gates having the advantage of allowing the voltage at
common node to swing the full logic values with the loading of
the common node as its disadvantage (col. 1, lines 66 through
col. 2, line 3). Additionally we observe that Calin teaches the
use of storage latch duplication and state-restoring feedback
circuits as viable design hardening techniques while recognizing
high chip area overhead and high power dissipation as its
drawbacks (page 2874). However, Calin points out that such
drawbacks may be tolerated in situations where reliability
prevails over the cost of increased die area (page 2874, last
paragraph of right hand column). Thus, contrary to Appellants’
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