Appeal No. 2006-1901
Application No. 10/742,436
Appellants argue that there is no motivation for combining
the references because both Jamshidi and Zhang teach away from
dual transistor designs in order to avoid increasing the die area
(brief, page 10). In particular, Appellants point out that
Jamshidi actually is related to eliminating dual transistor
design in a pass gate as it increases die area and power
dissipation (brief, page 11). Appellants further provide
arguments related to increased die area if the complementary pass
gate of Jamshidi is used in the latch design of Calin or Zhang
and conclude that no reasonable expectation of success supports
the combination (id.).
In response to Appellants’ arguments, the Examiner asserts
that using two transistors as the transfer gate, while taking up
more space, enhances the circuit reliability and minimizing the
failure rate (answer, page 5). With respect to Appellants’
argument regarding the lack of reasonable expectation of success,
the Examiner argues that the combination would be desirable since
it does increase the circuit reliability even though it is at the
expense of using more of the chip’s real estate (answer, page 8).
The Examiner adds that one skilled in the art would have been
willing to trade circuit size for a better performance if keeping
the chip area small results in inadequate performance (id.).
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