Appeal No. 2006-2382
Application 09/902,140
Claim 1 is simple and straightforward and we expect the
rejection to clearly point out where Wong '643 discloses each
step. Instead, the examiner has rephrased the issue as one of
determining convergence to a steady state behavior without
explaining how such determination would satisfy the claim
language of "(a) carrying out a first DC-simulation run at the
beginning of a functional cycle, (b) carrying out a second DC-
simulation run at the end of said cycle, (c) comparing simulated
values from both runs at respective circuit nodes." The examiner
states (EA10): "To determine whether circuit behavior has
converged to a steady-state requires a comparison of the same
circuit node over time (different DC conditions cause[d] by the
iterative charging or discharging of a circuit element in the
previous iteration in the circuit simulation[)]." However, this
does not explain the correspondence to the limitations of
"(a) carrying out a first DC-simulation run at the beginning of a
functional cycle," and "(b) carrying out a second DC-simulation
run at the end of said cycle." "Steady state" and "iterations"
do not imply DC conditions. Nor has the examiner pointed out
what corresponds to the "functional cycle." The examiner
interprets "that static error corresponds to the DC-simulation"
(EA3) without defining "static error" and without pointing out
where Wong '643 discusses static error, and we do not find the
word "static" mentioned anywhere in Wong '643.
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