Appeal No. 2006-2382
Application 09/902,140
Wong IEEE
Appellants argue that Wong IEEE does not do a DC simulation
of end of cycle conditions and does not store mismatch
information between two DC simulations corresponding to cycle
start and cycle stop (Br5). Thus, we look to see what the
examiner relies upon to meet these specific limitations.
The examiner again operates under the assumption that the
issue is whether the claimed invention reads on the prior art
teaching of determining whether a circuit has converged on a
steady state behavior. The examiner finds that Wong IEEE
discloses an iterative technique for steady-state analysis of
switching regulators using two iteration loops and, in
particular, Wong IEEE discloses DC analysis with error detection
and correction at Figs. 2-3 and the corresponding text (EA5). It
is stated that appellants have not addressed the specific
sections of Wong IEEE relied upon in the rejection (EA8).
We incorporate by reference our discussion of the examiner's
rejection over Wong '643. As with the rejection over Wong '643,
the examiner has not pointed out how the claim steps correspond
to the teachings of Wong IEEE. Wong IEEE is directed to an
iterative technique for computing the steady-state solution of
PWM (pulse width modulation) DC/DC switching regulators (p. 759).
We do not find any disclosure of performing a DC simulation at
the beginning and end of a functional cycle, or comparing the
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