Appeal No. 2006-2441
Application No. 10/056,224
1. At column 6, line 44 through column 7, line 5, Bunnell
states:
The microprocessor 20 communicates to the CPU activity
monitor 24 via a cache miss signal 36 and a plurality of mode
signals 38, 40, and 42, an address bus 32, and a data bus 34.
As explained in more detail below, the plurality of mode
signals include a read/write signal 38, a data/control signal
40, and a memory/IO signal 42 that communicate the operating
mode of the microprocessor 20. The cache memory system 30
generates the cache miss signal 36 when the microprocessor 20
must access the main memory 22. Whenever the CPU 28 requests
data, the cache memory system 30 checks to see if data already
exists in the cache memory system 30 (a hit). If the data does
not exist in the cache memory system 30 (a miss), the CPU 28
accesses the main memory 22. Thus, the cache memory system 30
generates the cache miss signal 36 when the CPU 28 accesses
data that is not stored in the cache memory system 30. The CPU
activity monitor 24 monitors the number of CPU activity events
that occur during a certain time interval. In the preferred
embodiment, the duration of the time interval has a range of
one to tens of milliseconds. The clock 26 which generates a
clock signal 44 is a system clock or a division of the system
clock. The CPU activity monitor 24 uses the cache miss signal
36, the clock signal 44, and the plurality of mode signals 38,
40, and 42 to generate an interrupt request 46. The interrupt
request 46 connects to the microprocessor 20 and initiates a
power system interrupt service routine.
2. At column 3, lines 24 through 42, Roeber states:
According to the invention, an event logging mechanism
is effected as a hybrid implementation having hardware and
software components. The event logging mechanism's hardware
component includes an off-the-shelf single board computer or
control card configurable onto a backplane containing the
target processor(s) being monitored. A high resolution clock
on the control card is used to time stamp events. A portion
of memory on the control card is used as a central buffer to
store event data, while another portion of memory on the
control card is used to store a control program that effects
functionality of the control card. The central buffer of
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