Appeal 2006-0016
Application 10/347,536
to specific pages and lines of the specification and reference characters of
the drawings. . . ." Ex parte Deshpande, No. 2006-0016, at 3 (B.P.A.I.
2006).
The Appellants responded by merely citing those pages and lines of
their specification that presumably relate to each claim. (Supp. Appeal Br.
5-8.) They failed, however, to address the mapping of each limitation of
the claims. Nor did they map anything to the drawings.
Furthermore, the Appellants' citations were broad. Regarding
claim 37, for example, they cited "page 54, line 16, through page 67, line 3,
and more particularly page 60, line 26, through page 61, line 18," (id. 5), of
their specification. Such citations have proven of minimal assistance in
deciding their appeal. We choose not to dismiss the instant appeal at this
time, nevertheless, and will endeavor to map the limitations to specific pages
and lines of the specification and to reference characters of their drawings as
best as we can.
A. INVENTION
The invention at issue on appeal is a "distributed system structure for
a large-way, multi-bus, multiprocessor system using a bus-based cache-
coherence protocol." (Specification 4.) According to the Appellants,
symmetric multiprocessing systems have been designed around a common
bus to which all processors and devices are connected. The common bus
serves as the pathway for transferring commands and data between the
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