Appeal 2006-0016
Application 10/347,536
Third, the Appellants note, "The specification also states that if the
processors block the ordinary protocol responses, no external logic is needed
to block colliding Read transactions. 'If the processors do implement the
RemStat-related requirements, then the processors may run without
inclusion, and no external logic is needed to detect the Read-Read collision
and to block colliding Read transactions.' See specification page 63,
lines 17-21." (Br. 5.) Although this part of the specification describes
blocking, it does not disclose that the processors perform the blocking. To
the contrary, the part teaches that the "blocking [is] implemented in the
bridge chip, e.g., the node controllers in the distributed, multi-bus,
multiprocessor system. . . ." (Specification 63: 14-16.)
For the aforementioned reasons, we agree with the Examiner's finding
that the Appellants' original disclosure fails to reasonably convey to the
artisan that they had possession, as of the filing date of their application, of a
processor that, after requesting a Read transaction, blocks transactions that
collide with its transaction. Therefore, we affirm the written description
rejection of claim 37 and of claims 38-48 and 60-65, which fall therewith.
III. ANTICIPATION AND OBVIOUSNESS REJECTIONS
The Examiner makes the following allegations.
Donaldson et al. disclose . . . abstaining by said processor from
going critical by blocking transactions that collide with said
Read transaction from being received by said processor during
processing of said transaction, in response to receiving, by said
processor, a coherency response indicating state information for
data to be read by the Read transaction will be delivered along
with delivery of the data, said processor and said other
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