Appeal 2006-0016
Application 10/347,536
processors and devices and for achieving coherence among the system's
cache and memory. (Id. at 1.)
The single-system-bus design also simplified the task of achieving
coherence among the system's caches. (Id.) More specifically, the
Appellants recognize two broad classes of cache-coherence protocols, viz.,
bus-based snooping protocols and directory-based protocols. (Id. 2.)
Although a single-system-bus design is currently preferred for implementing
coherence protocol, the Appellants assert that "it cannot be employed for a
large-way multiprocessor system." (Id. 3.)
In contrast, the Appellants’ invention organizes master devices into a
set of nodes supported by a node controller. The node controller receives
and queues commands received from master device and communicates
therewith. A bus protocol "reports the state of a cache line to a master
device along with the first beat of data delivery for a cacheable coherent
Read." (Id. 4.) "[T]he node controller helps to maintain cache coherency
for commands by blocking a master device from receiving certain
transactions so as to prevent Read-Read deadlocks." (Id.)
Claim 37, which further illustrates the invention, follows.
37. A method of maintaining cache coherency by prohibiting
Read-Read deadlocks in a multiprocessor system, the method
comprising the steps of:
requesting a Read transaction of a cache line by a
processor;
3
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