Appeal 2006-0016
Application 10/347,536
directory in main memory." (Abs. ll. 1-4.) "FIG. 1 is a block diagram of
[the] multi-processor system. . . ." (Col. 4, ll. 65-66.) The Figure shows that
"[e]ach one of several nodes, for example, four central processing
units (CPU's) 10, 11, 12 and 13 includes a write back cache memory 30 . . .
and is coupled by a channel 14, 15, 16 and 17, respectively, to a cross bar
switch unit 18." (Col. 5, ll. 15-19.) "Moreover, each of several (for
example, four) main memory modules 22, 23, 24, 25 is coupled by
channels 26, 27, 28 and 29, respectively, to the cross bar switch unit." (Id.
ll. 22-25.)
The part of Donaldson relied on by the Examiner describes a
"FORWARD-EXCLUSIVE," (col. 6, l. 42), ownership state of a "data block
residing in the main memory module 22-25." (Id. ll. 18-19.) In this state,
explains the reference, "[a]ny additional read commands to this block force
the main memory module 22-25 to stop processing all new read commands
until the outstanding Read Exclusive is completed." (Id. ll. 46-49.) Based
on this explanation, we agree with the Appellants that the FORWARD-
EXCLUSIVE state "does not describe blocking transactions that collide with
the Read transaction from being received by the processor during processing
of the Read transaction." (Reply Br. 3.) This state merely stops the
processing of new read commands.
The absence of blocking colliding transactions from being received by
a processor that requested a Read transaction negates anticipation.
Therefore, we reverse the anticipation rejection of claims 37 and 60 and of
claims 38-40, 42-48, 61-63, and 65, which depend therefrom. The Examiner
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