Appeal 2007-2016
Application 09/148,392
ISSUE
Appellant contends that Jyu’s transistor autosizing requires selecting
an entire circuit and does not disclose 1) design points on a parameter
function; 2) a parameter function having a first sum of a constraint set and a
second sum of an optimizing set; 3) selecting the initial design points; and 4)
selecting the new design points, as recited in the claims (Reply Br. 9-10).
The Examiner asserts that the portions of Jyu relied on in the rejection “are
all directed to analysis and improving the design using power and delay as
the constraining factors with scaling up and down based on costing function
responsive to changes in delay and/or power to yield an improved circuit”
(Suppl. Answer 17). The Examiner further argues that Appellant is using
well known technologies and methodologies to affect designs within a
circuit framework (id.).
The issue, therefore, is whether the Examiner erred in rejecting the
claims under 35 U.S.C. § 102(e). The issue specifically turns on whether
Jyu anticipates Appellant’s claimed invention by disclosing “selecting initial
design points on the parameter functions having a first sum of the constraint
set and a second sum of the optimizing set such that the first sum satisfies
the design constraints,” as recited in claim 1.
FINDINGS OF FACT
The following findings of fact (FF) are relevant to the issue involved
in the appeal and are believed to be supported by a preponderance of the
evidence.
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