Appeal 2007-2016
Application 09/148,392
1. Jyu relates to a method for minimizing signal delay and power
consumption through combined power simulation and delay analysis
resulting in iterative transistor resizing (Abstract). The method includes
sizing up a first transistor when its time delay normalized to the time delay
of greatest value exceeds a predetermined threshold value, and sizing down
the transistor when the normalized time delay is less than the predetermined
threshold value (col. 3, ll. 50-62).
2. Jyu provides for “Design goals” commands that facilitate three
execution modes of the transistor autosizing engine 320: requirement mode,
cost-function mode and slack-driven mode (default is cost-function mode).
In requirement mode, delay and power form the two requirement
parameters. If the delay requirement is specified (delay requirement mode),
engine 320 will first satisfy the specified delay and then minimize the power.
Conversely, if the power requirement is specified (power requirement
mode), engine 320 will first satisfy the specified power and then minimize
the delay. If both delay and power requirements are specified, the latter will
overwrite the former. In other words, the last requirement command in the
procedure will be executed and all previous requirement commands will be
ignored (col. 10. ll. 52-66).
3. As depicted in Figure 6 of Jyu, an initial circuit must be
selected in block 630 and controlled by the “design goals” commands, which
provide for three execution modes: requirement mode, cost-function mode
and slack-driven mode. In general, the circuit associated with the “best” size
for the controlling execution mode is chosen as the initial circuit and
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Last modified: September 9, 2013