Appeal 2007-2016
Application 09/148,392
set and a second sum of the optimization set. While the Examiner's
extensive explanation of the knowledge of one of ordinary skill in the art in
the Supplemental Answer is noted, the Examiner’s Answer is not prior art.
The prior art is Jyu, and it does not indicate that such analysis and design
improvement in the manner recited in the claims is well known in the art,
nor does it suggest the inherency of such features. See In re Yates, 663 F.2d
1054, 211 USPQ 1149, 1151 (CCPA 1981) (when the PTO asserts that there
is an explicit or implicit teaching or suggestion in the prior art, it must
indicate where such a teaching or suggestion appears in the reference).
The Examiner refers to the use of constraints and optimization in Jyu
and finds their use in designing a transistor size based on computing power
to be the same as the claimed first sum and the second sum (Suppl. Answer
18). While the transistor in Jyu is sized to satisfy both delay and power, we
agree with Appellant (Reply Br. 11) that it is not “inherent” or “well known”
to do so based on selecting initial design points on the parameter functions
having a first sum of the constraints set and a second sum of the optimizing
set. Nor has the Examiner identified in Jyu the ways to satisfy the design
constraints by a first sum of the constraint set, explicitly or implicitly.
Therefore, as the initial burden is not met by the Examiner, the burden of
going forward in rebuttal does not shift to Appellant. We also note
Appellant’s effort to address the Examiner’s position to the extent that such
position can be understood.
Under the facts we have here and the arguments presented by the
Examiner and Appellant, as described above, we have concluded that a
prima facie case has not been established.
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Last modified: September 9, 2013