Appeal 2007-2105
Application 10/762,445
pending in this application as claims 3 and 10 have been canceled. We have
jurisdiction under 35 U.S.C. § 6(b).
Appellants’ invention relates to a floating gate flash memory cell
having reduced drain induced barrier lowering (DIBL) and a sufficiently low
Vss resistance (Specification 2). Appellants provide for a recess formed in
the substrate adjacent to a stacked gate structure of the memory cell, where
the recess has a sidewall, a bottom, and a depth (Specification 3). The
source region is formed adjacent to the sidewall of the recess and under the
stacked gate structure while a Vss connection region is formed under the
bottom of the recess and under the source and connected to the source (id.).
According to Appellants, the Vss connection region under the bottom of the
recess, in addition to having a reduced resistance, reduces the DIBL by
lowering the lateral diffusion of the source in the channel region
(Specification 3-4).
Independent Claim 1 is representative and reads as follows:
1. A floating gate memory cell situated on a substrate, said
floating gate memory cell comprising:
a stacked gate structure situated on said substrate, said stacked
gate structure being situated over a channel region in said substrate;
a recess formed in said substrate adjacent to said stacked gate
structure, said recess having a sidewall, a bottom, and a depth;
a source of said floating gate memory cell situated adjacent to
said sidewall of said recess and under said stacked gate structure;
a Vss connection region situated under said bottom of said
recess and under said source, said Vss connection region being
2
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