Appeal 2007-2105
Application 10/762,445
remain undisputed by Appellants. However, Appellants argue that the Vss
connection region is at the same elevation level as the low concentration
source 7b and therefore, does not meet the claim language (Br. 8). The
Examiner responds by stating that “a small part of Hori’s ‘Vss connection
region’ 7a is situated under the bottom of the recess (14) and under the
source 7b” (Answer 9).
The memory cell disclosed by Hori includes a low concentration
source area that is positioned under the edge of the stacked gate between the
channel area and the high concentration source area (FF 1-3). The memory
cell further includes a high concentration source area which is shown in
Figure 1A as being between the low concentration source 7b and the recess
edge 15. Source 7a further extends to an area under the recess bottom 14.
The source region that is connected to the bit line or the Vss, as asserted by
the Examiner, is actually the high concentration area 7a (FF 4). Therefore,
while Hori refers to both regions 7a and 7b as “source” (FF 5-6); we agree
with the Examiner to the extent that Hori shows the Vss connection region
under the bottom of the recess.
However, as argued by Appellants (Br. 8), a portion of the Vss
connection region is adjacent to the recess wall and is positioned on the top
surface of the semiconductor substrate at the same elevation level as source
7b extending to an area near the floating gate stack (FF 6). In the specific
configuration of the Vss connection region disclosed in Hori, the region that
is situated adjacent to the sidewall of the recess is the Vss connection region,
and not the source, as required by the claim. Additionally, although it may
be situated below the source level, the Vss connection region situated under
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