Appeal No. 95-2599
Application 07/983,931
etch rate. Appellants disclose on pages 12 and 13 of the
specification that one physical feature difference between the
two layers which would allow for a different etch rate is grain
size. Appellants disclose that the upper and lower layers may be
formed of polysilicon wherein the grain size of the polysilicon
in the upper layer is different from that of the lower layer.
Appellants disclose on pages 13 and 14 of the specification that
another difference that would provide the lower layer 3a with a
faster etch rate than the upper layer 3b is ion impurity
concentration. Appellants disclose that by providing the upper
layer with a first ion impurity concentration and the lower layer
with a second ion impurity concentration wherein the second ion
impurity concentration is greater than the first ion impurity
concentration, the lower layer 3a will have a faster etch rate
than the upper layer 3b.
The independent claim 25 is reproduced as follows:
25. A field effect transistor comprising:
a semiconductor substrate having a main surface and a
pre-determined impurity concentration of a first
conductivity type;
impurity layers of a second conductivity type formed
spaced apart at the main surface of the semiconductor
substrate, said impurity layers constituting source-
drain regions, each of the impurity layers comprising a
first impurity layer portion having a first impurity
concentration and a second impurity layer portion
3
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