Appeal No. 95-1351
Application 07/547,630
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134 from the final rejection of claims 1-4, 6,
8-11, 13, and 15-20, all the claims pending in the application. The amendment after final rejection
received March 22, 1994 (Paper No. 17) has been entered.
The invention is directed to a processor system and a method of operating a processor system
having a cache and using load and store instructions for accessing a given location in memory. A
"FETCH" instruction prefetches a block of data including the given location in memory referred to
in the load or store instruction to a faster-access cache in the memory hierarchy before the data block
is to be used. This is described in the specification at page 9, lines 8-16, page 41, lines 24-25, and
page 42, lines 6-24. "The FETCH instruction is intended to help software bury memory latencies on
the order of 100-cycles" (specification, page 42, lines 21-22).
Claim 1 is reproduced below.2
1. A method of operating a processor system of the type having a CPU and a
hierarchical memory, the hierarchical memory having a faster-access part and a slower-access
part, wherein said faster-access part of said memory is a cache memory, the CPU having a
register set including a plurality of registers, comprising the steps of:
executing a sequence of instructions by said CPU, said sequence including a
load or store instruction for accessing a given location of said memory and for transferring
information between a selected one of said registers and said given location in said memory,
the step of executing said load or store instruction including sending an address from said
CPU to said memory on a bus;
executing in said sequence a prefetch instruction to move a block of data
including said given location from said slower-access part of said memory to said
2
It is noted that claim 19 in the claims on appeal depends on cancelled claim 7.
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