Appeal No. 95-1351
Application 07/547,630
Appellants argue that claims 1 and 8 "are distinguished from Kane by reciting that (1) that a
separate prefetch instruction (different from the load or store instruction) is executed before a load
or store in an instruction stream, and (2) the prefetch instruction does not alter the content of a
register" (Brief, page 5). We agree that both limitations are recited in claims 1 and 8 and that neither
limitation is found in Kane or Motorola. It is sufficient to just examine the prefetch limitation.
The examiner finds that "[a]lthough Kane did not specifically detail (claims 1,8) that a prefetch
which [sic] was executed one or more cycles ahead of time, Kane taught (e.g.,see p. A5) that there
was a latency of one instruction" (Examiner's Answer, page 3). The examiner concludes that "it
would have been obvious to one of ordinary skill in the DP art at the time of the invention that the
instruction which was prefetched must have been prefetched at least one or more cycles ahead of
when it was used or executed" (Examiner's Answer, page 4). The examiner's reasoning does not
address the actual claim language.
Claim 1 does not recite that an instruction was prefetched ahead of the time it was executed
as stated in the examiner's rejection. We agree that instructions in the cache are prefetched in
advance of their execution by the processor. Claim 1 recites "a prefetch instruction to move a block
of data including said given location [for access by a load or store instruction] from said
slower-access part of said memory to said faster-access part . . . said prefetch instruction being
executed a number of cycles prior to said load or store instruction." That is, claim 1 requires a
separate prefetch instruction, not just the prefetching of an instruction that occurs during normal
program execution. Furthermore, what is prefetched is a block of data including the memory location
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