Appeal No. 95-1351
Application 07/547,630
(claim 1), but only prefetches the next sequential instructions. Lastly, appellants are correct that the
examiner errs in finding that the burst mode is enabled by a bit in the cache control register being set
by the MOVE to CCR instruction. CCR stands for the condition code register, which holds condition
codes such as overflow, zero, not-equal-zero, etc. The cache control register is the CACR. It is true
that the CACR can be written or read by the MOVEC instruction (page 6-16), but the MOVE to
CCR is not the same as MOVEC. The MOVEC would have to be an instruction in the supervisor
program (pages 6-1, 6-16). It has not been shown that there is any mechanism for executing a
MOVEC instruction "a number of cycles prior to the load or store instruction" (claim 1). In any case,
as explained above, the burst mode does not cause a block transfer of data to cache until after there
has been a cache miss, so the MOVEC instruction cannot be a prefetch instruction as claimed.
- 7 -
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007