Appeal No. 95-1351
Application 07/547,630
The examiner further finds that Kane does not expressly disclose executing a prefetch
instruction that does not alter the contents of the registers (Examiner's Answer, page 4). The
examiner further relies on the teachings in Motorola. The examiner finds that Motorola teaches a
MOVE to CCR instruction (which the examiner states has a correct name of MOVEC) that alters a
cache control register which causes data to be fetched to the cache from main memory (burst mode
filling) (Examiner's Answer, page 4). The examiner seems to rely on the MOVEC instruction in
Motorola as being the prefetch instruction (Examiner's Answer, page 8). We conclude that Motorola
also fails to teach a prefetch instruction, as claimed. Therefore, Motorola cannot make obvious the
limitation of "said step of executing said prefetch instruction not altering the content of any of said
registers of said register set."
We agree with appellants' arguments that the examiner has misinterpreted Motorola.
Motorola states (page 6-1): "When appropriate, the bus controller requests a burst mode operation
to replace an entire cache line. The cache control register (CACR) is accessible by supervisor
programs to control the operation of both [instruction and data] caches." Therefore, the cache fill
is under the control of the bus controller whereas claim 1 requires executing the sequence of
instructions which includes the prefetch instruction on the CPU. In addition, the burst mode
operation occurs after a cache miss in an ordinary read cycle, not prior to any particular instruction.
Therefore, the burst mode does not operate as a prefetch instruction executed before (i.e., pre-) a
load or store instruction. Even if burst mode filling is considered a form of prefetch, it does not
prefetch a "block of data including said given location [for access by a load or store instruction]"
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