Appeal No. 95-1351
Application 07/547,630
faster-access part, the step of executing said prefetch instruction including sending an address
from said CPU to said memory on a bus, said prefetch instruction being executed a number
of cycles prior to said load or store instruction, said step of executing said prefetch instruction
not altering the content of any of said registers of said register set;
wherein said cache stores multi-word lines of data, and wherein said prefetch
instruction moves a block of data larger than one of said multi-word lines.
The examiner relies on the following references:3
Sachs et al. (Sachs) 4,884,197 November 28, 1989
Kane, MIPS R2000 RISC Architecture (Prentice Hall 1987), pages 1-1 to 4-11, A-1 to A-9.
(Motorola) MC68030 Enhanced 32-Bit Microprocessor User's Manual Second Edition
(Prentice Hall 1989), pages 3-111 to 3-115, 3-120 to 3-122, 6-1 to 6-17.
Claims 1, 3, 4, 6, 8, 10, 11, 13, and 15-20 stand rejected under 35 U.S.C. § 103 as being4
unpatentable over Kane and Motorola. Claims 2 and 9 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Kane and Motorola as applied in the rejection of claims 1 and 8 further in view of
Sachs.
OPINION
We reverse.
The examiner cites the paper by Chi et al., Compiler-Driven Cache Policy, Purdue3
University, June 1987, pages 1-54, in the Examiner's Answer, page 3, but does not mention it
further or apply it in any ground of rejection. Accordingly, the paper will not be further
discussed.
4
The Examiner's Answer lists claims 15, 17, 19, and 20 instead of claims 15-20. However,
since claims 16 and 18 are discussed (Examiner's Answer, page 5) it is assumed that the rejection
was meant to include claims 16 and 18.
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