Appeal No. 95-4714
Application No. 08/046,476
16 constitute the termination address (col. 34, lines 18-27). In
response to issuance of the flush command signal by MPU 702,
flush control is assumed by special purpose hardware, which under
the control of the internal sequence controller carries out the
flushing operation independently of direct control by the MPU,
retaining control until the last block has been flushed (col. 17,
lines 54-59; col. 32, lines 62-66). At the start of the flushing
operation, bits 6-14 of the start address are loaded into counter
718 (col. 60-63), which apparently is incremented each time a
cache block has been processed. Flush operation is terminated
when the address stored in the counter equals the termination
address appearing on local data bus 730 (col. 34, lines 54-57).
After the flush operation has been completed, the internal
sequence controller issues an acknowledge signal (ACK) to the MPU
(col. 36, lines 45-49). It is readily apparent that the above-
described special purpose circuitry functions as "flush control
logic means coupled to said address bus for controlling said
cache block flush operation after receipt of a flush command from
the central processor," as required by claim 13. The question is
whether it also satisfies the requirement that the control logic
means "issu[e] a signal and assert[] control of said address bus
after receipt of said flush command" and "retain[] control of
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