Appeal No. 95-4714
Application No. 08/046,476
the protection bit in the tag array element
corresponding to said first block of data is in a first
predesignated state; and,
the plurality of context bits in the tag array
element corresponding to said first block of data match
said plurality of context identifier bits.
The preamble is satisfied by Stiffler for the reasons given
above in the discussion of the preamble of claim 13. The
elements in the body of the claim correspond as follows to the
circuitry in Stiffler's Figures 1, 2, 7 and 8:
(a) "main memory" - elements 165, 170, 175, and 184.
(b) "memory management unit" - MMU 210 in Fig. 2.
(c) "virtual cache data array" - cache memory 250 in Fig. 2.
(d) "virtual cache tag array . . . for storing a plurality
of cache tag element" - block status memory 255 in
Fig. 2.
(e) "each tag array element including . . ."
(1) "a validity bit" - "valid" bit (col. 9, lines 27-
31).
(2) "a modification bit" - "dirty" bit (col. 9, lines
31-35).
(3) "a protection bit" - discussed below.
(4) "a write allowed bit" - discussed below.
(5) "a plurality of virtual address field bits" - the
address "label" stored in the block status memory
(col. 13, lines 36-42).
(6) "a plurality of context bits" - discussed below.
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