Appeal No. 95-4714
Application No. 08/046,476
required of the "flush control logic means."
The next paragraph, which calls for "reset means coupled to
said flush control logic means for setting and resetting elements
of said cache blocks tags," reads on the step of invalidating the
Valid bits in the cache tags as part of the flushing process
(Spec. at 11, lines 5-7).
Skipping over the next paragraph for a moment, the last
paragraph requires a memory management unit coupled to the cache
array for reassigning virtual addresses to the plurality of cache
blocks after the flush operation is complete. This paragraph
accurately describes the function of appellants' MMU 27 (Spec. at
19, lines 10-18).
The claim paragraph which is the basis for the § 112
rejections reads as follows:
a plurality of cache flush control means disposed
within said kernel of said shared, multi-user operating
system and responsive to said signal issued by said flush
control logic means, each of said flush control means
comparing preselected portions of said cache block address
and elements of said cache block tag for each of said
plurality of cache blocks to different preselected criteria,
said flush control means then flushing said cache blocks to
said main memory if said comparison results in a preselected
relationship. [Emphasis added.]
The problem is that the claimed functions are disclosed as being
performed by hardware rather than by the operating system
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