Appeal No. 95-4714
Application No. 08/046,476
on the disclosure in the following manner. The CPU issues a
Flush command that is described as follows in the paragraph
bridging pages 28-29:
The Flush command is issued by the CPU in Control Space
(identified by Function Code bits FC(2:0)=0x3). Within
Control Space, the four high order address bits A(31:28)=0xA
indicate the Flush command. The address field A(27:0) for
the command correspond to the 28 bit virtual address field
for data accesses. The Flush command data bits D(1:0)
encode the type of flush.
The types of flushes include context, page, and segment (Spec.
at 28, lines 15-17).
The Flush command address and data bits are provided as
input signals to the cache flush block diagram shown in
Figure 11, which represents the operation of cache flush logic 33
of Figure 1 (Spec. at 28, lines 3-4). This logic includes an AND
gate 48, flip-flops 49, flush address register 52, incrementer
50, AND gates 55, and OR gate 58 (Spec. at 28, lines 7-9). The
specification explains (at 29, lines 6-9) that “[a]fter the Flush
command is decoded [by AND gate 48], the address field A(27:9) is
latched [in flush address register 52] together with the type of
flush [in flip-flops 49]. A Bus Request signal is asserted to
the CPU to obtain bus mastership.” The CPU then issues a Bus
Grant signal to the flush control logic, which retains control of
the cache address bus until after the last of the cache blocks
- 5 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007