Appeal No. 95-4714
Application No. 08/046,476
entry by the examiner, it has not been considered.
The invention is a flushing system for a virtual cache
memory in a computer workstation. Claim 13, which is one of the
three independent claims on appeal (claims 17 and 23 are the
others), reads as follows:
13. In a computer workstation operating in
accordance with a shared, multi-user operating system
having multiple concurrently active contexts and having
a kernel wherein virtual addresses are assigned for
each of a plurality of users, said workstation having a
central processor and a cache data array coupled to an
address bus, said cache data array including a
plurality of cache blocks each one having a cache block
address and an associated cache block tag, a system for
completing a cache block flush operation, comprising:
flush control logic means coupled to said address
bus for controlling said cache block flush operation
after receipt of a flush command from said central
processor, said flush control logic means issuing a
signal and asserting control of said address bus after
receipt of said flush command, said flush control logic
means retaining control of said address bus until said
cache block flush operation is completed;
reset means coupled to said flush control logic
means for setting and resetting elements of said cache
block tags;
a plurality of cache flush control means disposed
within said kernel of said shared, multi-user operating
system and responsive to said signal issued by said
flush control logic means, each of said flush control
means comparing preselected portions of said cache
block address and elements of said cache block tag for
each of said plurality of cache blocks to different
preselected criteria, said flush control means then
flushing said cache blocks to said main memory if said
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