Appeal No. 95-4714
Application No. 08/046,476
said address bus until said cache block flush operation is
completed." We believe it does, when the recited "address bus"
is read on the address bus (737) that is directly connected to
the input of cache RAM 738. At the start of the flushing
operation, the internal sequence controller, acting through
multiplexers 720 and 726, causes bits 5-14 on this address bus to
be controlled by counter 718 (col. 34, lines 34-36). This
counter thus controls addressing of the cache until the flush
operation is complete.
The claimed "reset means" is also satisfied. When the flush
is being done as part of a context switch, the "valid" bit in the
block status memory will be cleared (col. 34, lines 8-10).
Skipping over the next paragraph, which we have determined
is indefinite, the claimed "memory management unit" reads on MMU
200 in Figure 23, the details of which are shown in Figure 8
(col. 3, lines 49-51).
The § 103 Rejection of Claims 17-27
Claims 17-27 stand rejected under § 103 as unpatentable over
Stiffler in view of Freeman. Claim 17 reads as follows:
17. A computer system with cache flushing
comprising:
a central processing unit operating in accordance
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