Appeal No. 95-4714
Application No. 08/046,476
Stiffler's flush control circuitry, which he describes as
"special purpose hardware" (col. 17, lines 56-57) and which
flushes one or more blocks from the cache data array in response
to a context switch or an overflow situation (col. 2, lines 8-
11). The flush control circuitry is controlled by the internal
sequence controller (unnumbered in Fig. 7 but identified by
numeral 700 in the specification), which causes the processing
element to assume one of eight operating states (col. 16, lines
4-5). The flushing operation that occurs during a context switch
is described in general at column 17, line 50 to column 18, line
3 and in detail at column 32, line 54 to column 36, line 49. The
operation begins with MPU 702 commanding a between-limits flush
(col. 17, lines 59-60). This command is in the form of an
address signal having the format shown in line G1 of Figure 9
(col. 33, lines 63-65). Bits 7-16 identify the cache block at
which to begin the flush operation (col. 33, lines 67-67). Bits
1-3 are control bits, of which bit CXT is set to zero to indicate
that the flush is being done as part of a context switch
(col. 34, lines 6-13). All of these bits (1-3 and 7-16) are
placed on the local address bus 730 (col. 33, lines 60-68). The
MPU also generates, on local data bus 732, a termination address
having the format shown in line G2 of Figure 9, of which bits 7-
- 12 -
Page: Previous 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Next
Last modified: November 3, 2007