Appeal No. 95-4714
Application No. 08/046,476
(f) "cache hit logic means" - internal sequence controller
700 in Fig. 8 (col. 22, lines 37-40).
(g) "cache flush logic means" - the circuitry of Figs. 7
and 8.
(h) "a context match flush command comprising a plurality of
context identifier bits" - discussed below.
(I) the cache flush logic means causes flushing if the
protection bit is in a first designated state and if the
context bits in the tag array elements match the context
bits in the context match flush command - discussed
below.
Regarding the "context" limitations, the examiner contends
(Answer at sec. 11g) that
Stiffler by necessity must identify which context is
currently active, since context switching is provided for,
so Appellant's claimed "context identification registers"
[sic, "context identification register" ] is not patentably4
distinguishing, since it is well known in the art for
registers to store identification data.
Even assuming for the sake of argument that the examiner's
reasoning is correct, the only purpose served by such a register
would be to keep the MPU apprised of the identity of the context
that is currently running. The examiner has not explained, and
it is not apparent to us, why this reasoning would have led the
artisan to additionally include context identification bits in
the block status register and in the flush command signal, as
4See dependent claims 21, 22, 26 and 27.
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