Appeal No. 96-0113
Application 07/848,779
"graphics generator" 10 in Figure 6 is an input device
such as a personal computer programmed to generate
graphics, not a device to generate the bit patterns. .
. . The generation of the bit patterns used in the
memory 34 is described in the specification at Col. 5,
line 42 to Col. 6, line 28.
We also agree with the appellant that there is nothing to
show that the computer program in Appendix A of Sullivan '501
generates or calculates all of the bit patterns simultaneously.
The fact that a supercomputer has been employed in Sullivan '501
does not mean the bit patterns are generated simultaneously. A
supercomputer possibly may have sufficient computing power to
generate the bit patterns simultaneously, but that does not
constitute a teaching, for anticipation purposes, that
simultaneous generation of bit patterns in fact is done. The
examiner is erroneous in finding that Sullivan '501 "provides the
'simultaneously' function as recited in the claims" (supplemental
answer at page 2).
For the foregoing reasons, we will reverse the rejection of
claims 1-7 and 11-18 under 35 U.S.C. § 102 as being anticipated
by Sullivan '501.
The rejection of claims 1-7 and 11-18
under 35 U.S.C. § 103 as unpatentable
over Daly or Sullivan '517, in view of Parker
On page 4 of the answer, the examiner states that the
obviousness rejection "is set forth in the prior Office action
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