Appeal No. 95-3497
Application 08/158,649
rejected claims and thus recite allowable subject matter (Answer
at 1 ). Claims 1 and 2 have been canceled. We reverse.3
The invention relates to an adder that can be used to
operate in parallel on a plurality of sub-words. Figure 1 shows
two N-bit operands 12 (X) and 14 (Y) each having two sub-words
(17-20) for processing by adder 10, which outputs a result word
16 (Z) having two sub-words 21 and 22. Figure 2 shows a pair of
single-bit adders 31 and 32 separated by a blocking circuit 33,
which prevents a carry if the masking signal M indicates that
k
these two adders are located on opposite sides of the boundary
separating two sub-words (Spec. at 5, line 18, to 6, line 14).
Figure 3 shows a 4-bit adding section 100 having multiplexers
121-124 which permit the sum bits (e.g., S ) of the resultant sum
q
signal to be selectively effectively shifted by one bit position
in order to divide the sum signal by two, i.e., to achieve
averaging. Referring to multiplexer 122, for example, when the
averaging signal A is true, the multiplexer provides bit S as
q+3
output bit Z ; when the averaging signal is false, the
q+2
multiplexer provides sum bit S as output bit Z (Spec. at 9,q+2 q+2
lines 1-5). When a shift occurs (i.e., when average signal A is
3We note, however, that these claims are now in
independent form and thus not properly objected to (Answer at 1)
for depending on rejected base claims.
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