Appeal No. 95-3497 Application 08/158,649 true), multiplexer 121 for the most significant bit position provides the carry signal C as output Z (Spec. at 9, linesq+3 q+3 13-15). The disclosed circuitry can also be used to subtract sub-words and divide the result by two (see claim 5). The references relied on by the examiner are: Gerrath 4,789,953 Dec. 06, 1988 Patti et al. (Patti '975) 5,047,975 Sep. 10, 1991 Patti et al. (Patti '636) 5,189,636 Feb. 23, 1993 A. The rejection of claim 5 Claim 5 reads as follows: 5. An apparatus for operating on the contents of an X word having bits X and a Y word having bits Y to generate a resulti i word having bits Z where i=0 to N-1, where Z is the leasti, 0 significant bit of one of said sub-words and Z is the most N-1 significant bit of one of said sub-words, said apparatus comprising: means for partitioning said X, Y and result words into a plurality of sub-words, there being one sub-word of said Y and result words corresponding to each sub-word of said X word; means, responsive to a first instruction, for generating the sum of each X sub-word and the corresponding Y sub-word, the result thereof determining said corresponding sub-word of said result word; and means, responsive to a second instruction, for generating the difference of each sub-word in said X word and the corresponding sub-word in said Y word, the result thereof determining said corresponding sub-word of said result word; and means, responsive to a third instruction, for generating the difference divided by two of each sub-word in said X word and the corresponding sub-word in said Y word, the result thereof determining said corresponding sub-word of said result word. - 3 -Page: Previous 1 2 3 4 5 6 7 8 9 10 11 NextLast modified: November 3, 2007