Appeal No. 95-3497
Application 08/158,649
examiner contends that it would have been obvious to use
Gerrath's adder 8 and shifter 13 in Patti's adders "because these
features are well-known in the data processing device" (Answer at
3-4). According to the examiner, Gerrath discloses "sum divided
by two" in the equations at column 3, line 40 (Answer at 4-5).
We agree with Appellants that the examiner's reliance on
Gerrath's adder 8 and shift register 13 is misplaced. Gerrath's
adder 8 is part of a circuit that calculates an output value Yn
in accordance with the formula Y =Y (1-% )+% X , where X is then n-1 n n
current value of the input signal at time t % is a factor which
n,
determines the transient response of the filter, and Y is the
n-1
output value calculated at time t (col. 1, lines 55-63).
n-1
Furthermore, as shown in Figure 1, one output value (Y , Y , Y ,n1 n2 n3
etc.) is calculated for each interval between transitions of the
input waveform X. At each transition of the input waveform, the
output value Y for the preceding interval is entered into shift
n
register 13, which has a number of stages equal to the number of
transitions in one period of the input waveform or a multiple of
one period of the input waveform (col. 5, lines 1-10). The
output values Y which are currently stored in the shift register
n
are combined in an adder to form an arithmetic sum of those
output values, which sum is divided in divider stage 15 by a
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Last modified: November 3, 2007