Appeal No. 95-3497
Application 08/158,649
Claim 5 stands rejected under 35 U.S.C. § 103 as
unpatentable for obviousness over the adder shown in Figure 4B of
Patti '975 or Patti '636. This adder, which includes two 8-bit4
adder circuits 450 and 452, is selectively operated to perform
either a conventional ADD operation or a dual-add-with saturate
operation (Patti '975, col. 15, lines 38-43) in order to
accommodate video signals in either of two different formats.
Specifically, when the SPLIT signal is false, the adder is used
to sum two conventional 16-bit two's complement values A and B,
with the eight least significant bits (8LSB) being summed in
adder circuit 452, the eight most significant bits (8LSB) being
summed in adder circuit 450, and the carry-out terminal CO of
0
adder circuit 452 being connected by AND gate 454 to carry-in
terminal CI of adder circuit 450. On the other hand, when SPLIT
1
is true, the adder is used to sum two input words each having an
8-bit sub-word representing an unsigned binary value and another
8-bit sub-word representing an 8-bit offset-128 value (col. 16,
lines 13-26). More particularly, the modified sum produced by
each 8-bit adder circuit is an 8-bit unsigned binary value
representing the sum of the input 8-bit unsigned binary value and
4While Patti '636 is a continuation-in-part of Patti '975,
the examiner relies only on commonly disclosed subject matter.
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